Flash memory, which is one form of nonvolatile semiconductor memory, has attractive features, such as a faster operational speed and lower power consumption. These features enable use of these devices in portable systems, such as digital still cameras and personal computers, with advanced data reliability and enhanced power maintenance.
Typical construction of a cell (or cell transistor) used to form a flash memory device is shown in FIG. 1. Such a cell can be used to form a multi-bit storage device. Source 3 and drain 4, each being formed of an N+ diffused region in a P+ semiconductor substrate 2, are separated from each other by a channel region which is also defined in substrate 2. Floating gate 6 is formed over the channel region. A thin insulating film 7, which is under 100 .ANG., isolates the floating gate 6 from the channel region. Insulating film 9, such as an O--N--O (Oxide-Nitride-Oxide) film, on floating gate 6 isolates a control gate 8 from the floating gate 6. Source 3, drain 4, control gate 8 and substrate 2 are each connected to corresponding voltage sources Vs (drain voltage), Vd (source voltage), Vg (gate voltage) and Vb (bulk voltage), for programming, erasing and reading operations.
A selected memory cell is programmed by means of hot electron injection between the channel region and the floating gate 6, in which the source 3 and substrate 2 are held at a ground voltage potential, a high voltage (e.g., Vg=10V) is applied to the control gate 8 and a voltage to induce the hot electrons therein, about 5V to 6V, is provided to the drain 4. Once programmed, a threshold voltage of the selected memory cell is increases due to the deposition of electrons. To read data from the programmed cell, a voltage of about 1V is applied to the drain 4, a power source voltage (or about 4.5V) is applied to the control gate 8, and the source 3 is held at the ground voltage. Since the increased threshold voltage of the programmed memory cell acts as a blocking potential even upon the gate voltage during a read-out operation, the programmed cell is considered an off-cell which has a threshold voltage between 6V and 7V.
Erasing a memory cell is accomplished by conducting F-N (Fowler-Nordheim) tunneling effect, in which the control gate 8 is coupled to a negative voltage of about -10V, and the substrate 2 (or bulk) to a positive voltage of about 5V, in order to induce the tunneling therebetween. As a result, the drain 4 is conditioned at a high impedance state (or a floating state). A strong electric field between the control gate 8 and bulk region 2 is induced by the voltage bias conditions and causes the electrons to move into the source 3. The F-N tunneling normally occurs when an electric field of 6.about.7MV/cm is developed between the floating gate 6 and bulk region 2, which are separated by the thin insulating film 7. The erased cell has a lower threshold voltage than before, and is therefore sensed as an on-cell which has a threshold voltage between 1.about.3V.
In a usual architecture of a memory cell array in a flash memory, the bulk region (or the substrate) combines active regions of memory cells, so that memory cells formed in the same bulk region are spontaneously erased at the same time. Therefore, units of erasing (hereinafter referred to as "sector", for instance, one sector of 64K) are determined in accordance with the number of separate bulk regions 2. Table 1 shows levels of the voltages used in programming, erasing and reading.
TABLE 1 ______________________________________ operation mode Vg Vd Vs Vb ______________________________________ programming 10V 5 .about. 6V 0V 0V erasing floating10V floating 5V reading 1V 4.5V 0V ______________________________________
As shown in FIG. 2, the range of voltage levels to detect a threshold voltage of a memory cell, which is applied to the control gate 8 through a word line, is preferably in the range of 3.about.6V (Vg; 4.5V in the table 1). If a selected memory cell has been programmed, a memory cell selected in the read operation is detected as the off-cell for the control gate voltage Vg. On the contrary, an erased cell is detected as the off-cell.
It is well known that a NOR-type flash memory features a higher read-out performance, i.e. access speed under 100 ns, than that of a NAND-type flash memory. The need for lower power consumption in portable devices forces memory products to operate with a lower power supply voltage, such as 3V, 2V or less. The gate voltage between 3V and 6V, required for reading, is regarded as a preferred value adaptable to such low power flash memories. The high voltages, as shown in Table 1, required for the programming and erasing operations are generated from internal boosting circuits (or pumping), which generate higher voltages than the power supply voltage (2V or 3V). In general, there needs to be at least two times more pumping cycles to generate the high potentials, 10V or -10V, which are applied to the control gate 8 for programming or erasing, and thereby a predetermined time to reach up to the appropriate voltage levels is required. In order to obviate a delay of the read-out operation, conventional flash memory devices always operate the pumping cycles in an independent operating mode so that the pumped voltage can be promptly applied to activated circuits assigned to the read-out operation. However, since the pumping voltage is being generated whenever the device is powered up, current consumption in a standby state is inevitable and thereby unnecessary power dissipation may occur.
An activation timing cycle of the pumping circuit is generally designed in correspondence with a nominal operation timing of the read-out cycle. Hence, under the designed features between the activation of the pumping circuit and read-out cycle timing, the pumping voltage may be consumed to concentrate current dissipation when an address transition occurs with an abnormal cycle time shorter than a specified read-out cycle time (e.g., tRC). Under extreme conditions, the amount of current dissipated for the address transition can be larger than that supplied from the pumping circuit, and, even worse, the pumping voltage could be lower than the appropriate voltage level for reading (e.g., 3.about.6V or 4.5V of Table 1). This condition can result in unreliable operation.
Furthermore, the conventional pumping circuit is not free from noise occurring in a read-out operation. The noise is induced from the pumping circuit which is designed to conduct according to normal read-out cycles, and not supplying current to internal circuits when address signals are varied (i.e., address transitions). Thus, it may be impossible to compensate dissipated current in the case of mismatching between the address transition and the oscillation cycle of the pumping circuit.